Loic Vezier

Loic Vezier is currently the SoC Design Manager at Silicon Mobility since December 2015. Prior to this, Loic worked at Scaleo chip as the AxEC/FPGA/Tools Technical Lead from May 2004 to December 2015 and as a Senior SoC/FPGA Design Engineer. Loic also has experience working as an Ingénieur en micro-électronique at Actsoft from November 2001 to April 2004. Loic holds a degree in Ingénieur en informatique des systèmes embarqués from ISIMA, obtained in 2001.