Hooi Kar

Hooi Kar is currently the Principal Architect at SkyeChip, where they define next-generation I/O interfacing IP such as UCIe, PCIe, and CXL. They have extensive experience in PCIe architecture, having worked at Intel Corporation from 2012 to 2016 in various roles, including Microarchitect Component Design Engineer and Overall Lead Microarchitect. Hooi has a deep understanding of logical and analog PHY interoperation and has achieved multiple patent filings throughout their career. They earned a Bachelor of Engineering in Electrical and Electronics Engineering from Universiti Tenaga Nasional from 2000 to 2004.