James Yang

James Yang is a Principal Engineer at SkyeChip, specializing in memory BIST, scan DFT, and automation scripting. With 15 years of experience in RTL design and 2.5 years focused on CPU memory BIST/BISR, James has held roles at Intel Corporation as a Senior Engineer, leading multiple projects and teams to enhance testing processes. Prior experience includes significant contributions at TSMC as a Digital Design Engineer, where they served as Tapeout Leader for memory validation testchips. James holds a Master of Engineering in Electrical and Electronics Engineering from National Chiao Tung University and is actively learning about AI and Machine Learning to improve team efficiency.