Devaraj Y J

Devaraj Y J is a Lead FPGA Engineer at SmartDV Technologies, where they focus on FPGA pre and post-silicon validation. Previously, Devaraj worked as a Debug Engineer at Tejas Networks, specializing in debugging SDH, SONNET, OTN, and Ethernet products, and served as an Engineer at L&T Technology Services Limited, where they handled USB Controller IP FPGA validation. Devaraj holds a Diploma in Electrical, Electronics, and Communications Engineering from K V T Polytechnic College and a Bachelor of Engineering from Nagarjuna College of Engineering and Technology.