Jithendra Chaluvadi is currently a Design Verification Engineer at SmartDV Technologies, specializing in high-speed bus protocols, particularly Compute Express Link (CXL). They have developed test scenarios for various CXL protocols and worked on the CPI interface, connecting the CXL VIP with CXL Controller IP to verify functionality. Previously, Jithendra interned at N Space Tech in 2023 and earned a Bachelor of Engineering in Electronics and Communications Engineering from R.M.K Engineering College, graduating in 2023 with a commendable GPA of 9.13.
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