Hever Arellano is an experienced System Debug Software Engineer currently at Solidigm since June 2023, with a prior tenure at Intel Corporation from August 2016 to May 2023, where roles included System Debug Software Engineer, System Validation Engineer, and Pre-Silicon Validation Engineer in the Non-Volatile Memory Solutions Group. Earlier experience includes positions as Materials Manager and Professor at Instituto Tecnológico de Nuevo León, a Sr Product Engineer at Oracle focused on Sparc Mseries Servers, and a Senior Hardware Engineer at Motorola Mobility. Hever's educational background includes a Master's Degree in Master of Engineering Technology with a focus on Mechatronic Engineering from Tecnológico Nacional de México, outstanding results in the National Certification Exam for Electrical and Electronics Engineering, and an Engineer's degree in Electrical and Electronics Engineering from Universidad Tecnológica de la Mixteca.
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