Jade Pascual is an accomplished SSD Validation Architect at Solidigm, with extensive experience in validation engineering across multiple leading technology companies. Previously held positions include Principal Validation Design Engineer at Microchip Technology Inc., where responsibilities involved test plan development and automation for the Microsemi Flashtec NVRAM product family, and Staff SSD Validation Engineer at Toshiba America Electronic Components, Inc., focusing on NVMe and SATA SSD testing. Additional roles include Staff Firmware Test Engineer at QLogic Corp., Senior System Validation Engineer at PMC Sierra, System Design Validation Engineer at Agilent Technologies, and Firmware Engineer at Hewlett-Packard. Jade holds a Bachelor of Science degree in Electrical Engineering and a minor in Computer Science from California Polytechnic State University-San Luis Obispo.
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