Adarsh Kumar is a Senior RTL Design Engineer at Spanidea Systems, where they focus on advanced design projects. They previously worked as an R&D Engineer at Qbit Labs, contributing to the development of PCIe Gen6 Protocol Analyzer for Xilinx Ultrascale+ FPGA. Adarsh graduated from the National Institute of Technology Patna in 2021 with a B.Tech in Electronics and Communication Engineering and is currently working as a contractor at AMD within the Ethernet IP Design Team.
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