Anshul Garg is a Memory Design Engineer currently working as a Technical Leader at STMicroelectronics since 2023. They have previously held positions as a Design Engineer consultant at Arm from 2018 to 2019, and as a Design Engineer at Sankalp Semiconductor Pvt Ltd from 2017 to 2019, where they trained in VLSI concepts and completed a project on SRAM circuit design. Anshul also served as an R&D Engineer at Synopsys Inc from 2019 to 2021, focusing on memory design. They are pursuing a Bachelor of Technology in Electronics and Communication Engineering at Jaipur Engineering College and Research Centre.
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