Anuj Varshney is a Technical Leader at STMicroelectronics, where they specialize in 5G L1 design and FPGA design. With extensive expertise in signal processing, Anuj has a solid background in the design and implementation of the complete PDSCH Layer in 5G, as well as significant experience in FPGA architecture and digital communication systems. Previously, Anuj held positions as a Technical Lead at Nokia and as a Hardware Engineer for the Ministry of Defence, contributing to various projects involving FPGA design and signal processing. Anuj earned foundational experience in FPGA and RTL design during their traineeship at PINE TRAINING ACADEMY.
This person is not in the org chart
This person is not in any teams
This person is not in any offices