Ayush Vyas is a Senior Design Engineer at STMicroelectronics, leveraging a Master's degree in VLSI Design. With experience as a Hardware System Engineer at System Level Solutions (India) Pvt. Ltd. from 2019 to 2021, Ayush worked on various FPGA development projects and gained knowledge in High Level Synthesis. Prior to that, Ayush interned at Kasura Technologies Private Limited, focusing on implementing protocols such as I2C and USB. Ayush possesses a solid background in SOC and FPGA domains, along with expertise in Cadence tools and Transaction Level Modeling.
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