Benoit V.

Benoit V. is an Analog Designer and Ingénieur validation at STMicroelectronics since September 2018, with responsibilities in testing and validating in the RF millimetre waves lab. Prior experience includes an interim role at STMicroelectronics in July 2017, providing cleanroom technicians with tools and parts, and an interim position at SITA NEWS in July 2016, coordinating appointments with job sites and waste disposal facilities for waste collection schedules. Additional experience includes working as a manutentionnaire at LEBON ET VERNAY in July 2015, focusing on packaging registers. Benoit V. holds an engineering degree in microelectronics from Grenoble INP - Phelma (2018-2021), a GEII degree from Université Grenoble Alpes (2016-2018), and a Baccalauréat in physical sciences from Ferdinand-Buisson (2013-2016).