Caffey Jindal

Caffey Jindal, PhD, has extensive experience in the field of VLSI and analog design. Initial training at A.Tech Labs involved working with 8051 microcontrollers. As a Lead Engineer at HCL Technologies, Caffey contributed to analog IO design for Cadence Design Systems, focusing on various components of DDRIO. Academic roles include positions as a Teaching Assistant and Research Scholar at Thapar University, focusing on circuit design and layout of analog building blocks, along with serving as a Senior Research Fellow at the Council of Scientific and Industrial Research. Caffey's academic credentials include a PhD in VLSI and a Master of Technology in VLSI from Thapar Institute of Engineering and Technology, both achieved with top CGPA scores. Currently employed as a Senior Design Engineer and Technical Lead at STMicroelectronics, Caffey continues to advance expertise in the industry.