Chirag Agarwal is a Sr. CAD/PDK Design Kit Engineer at STMicroelectronics, where they focus on PDK development and design rule checks. Their journey began at the Indian Institute of Space Science and Technology, where they earned a Master's degree in VLSI and Microsystems. Chirag has previously contributed as a Hardware Developer at Secure Meters Limited and as a Signalling and Telecommunication Trainee with Delhi Metro Rail Corporation. Their experience includes validating DRC decks through SKILL automation and supporting various technology node projects. With a strong foundation in both academia and industry, Chirag continues to push the boundaries of microelectronic design.
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