Gyanender Verma has over 15 years of experience in the semiconductor industry, specializing in memory layout design and project management. Gyanender began the career at ST Microelectronics as a Senior Design Engineer in the SRAM Memory Layout team from August 2006 to July 2012, followed by a role at LSI Research & Development as a Senior Design Engineer between July 2012 and October 2013. Gyanender then contributed to ARM as a Senior Layout Designer until February 2017. After that, Gyanender returned to ST Microelectronics as a Senior Project Manager in August 2022, having held positions at Synopsys Inc from October 2018 to July 2022 as both A&MS Layout Design Manager I and Senior II Layout Design Engineer, focusing on Memory Layout.
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