Jerome Lescot is a Senior Member of Technical Staff at STMicroelectronics, where they have worked since 2003. With over 20 years of experience in CAD development and support for analog design, they focus on reliability checks at the transistor level and are currently responsible for developing innovative solutions using advanced machine learning techniques. Prior to STMicroelectronics, Jerome served as a Corporate Application Engineer at Cadence Design Systems, where they specialized in specifications for new solutions related to RLCK parasitic extraction and 3D Si-substrate modeling. Jerome holds a Doctor of Philosophy in Electrical, Electronics, and Communications Engineering with honors from Grenoble INP - Phelma, earned in 1999.
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