Jyoti Sinha is a Lead IO Layout Engineer at STMicroelectronics, specializing in analog layout design with expertise in 7nm and 12nm FinFET processes, as well as 22nm FDSOI and 28nm Bulk technologies. With a background that includes roles at companies such as AMD and Xilinx, Jyoti has developed a strong proficiency in automation languages like SKILL, Perl, Python, and Shell, and has experience with key tools including Cadence Virtuoso and Calibre. Jyoti holds a Bachelor of Technology in Electronics and Communications Engineering from SHRI RAMSWAROOP MEMORIAL COLLEGE OF ENGINEERING AND MANAGEMENT and has further academic experience at Mount Carmel College, India.
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