Nitin Patel is a Senior Staff Engineer at STMicroelectronics, specializing in Physical Design Verification and IO Ring Design. They have extensive experience with various tech nodes and have worked as an AMS Layout Engineer and Design Engineer at notable companies, including NXP Semiconductors and TSMC. Nitin has contributed to the development of several analog and digital IPs and has proficiency in tools such as Calibre DRV and Cadence Virtuoso. Their work encompasses responsibilities like floor planning, placement, routing, and verification.
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