Pasquale Cesarano is a HW Design Engineer at STMicroelectronics since September 2023, having previously completed an internship with the company from February to July 2023, where the focus was on a master thesis involving the development and evaluation of alternative design methodologies for managing clock gating cells during the scan test of digital circuits. Pasquale holds a Laurea triennale in ingegneria elettronica obtained from Università degli Studi di Salerno in 2019 and is currently pursuing a Studente Magistrale in ingegneria elettronica at the same institution, expecting to enhance expertise in the field of electronic engineering.
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