Pradeep Munagala has seven years of experience in physical design, static timing analysis (STA), and formal verification. They previously worked at Folik Technologies from 2018 to 2021, where they focused on physical design and formal verification. From 2021 to 2023, Pradeep served as a Senior Engineer at SeviTech Systems Pvt. Ltd., gaining expertise in synthesis and timing analysis. Currently, Pradeep is a Technical Leader at STMicroelectronics, working on 7nm netlist-to-GDS conversions and physical verification checks.
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