RaghubeeR S.

RaghubeeR S. is a Principal Engineer specializing in Automotive ASIC chip design at STMicroelectronics as of 2024, bringing over 16 years of progressive experience in VLSI design, including synthesis, static timing analysis (STA), and RTL design. Previously, RaghubeeR held positions such as Senior Technical Lead at HCL Technologies, Staff Engineer at Microsemi Corporation, and Member of Technical Staff at Cadence Design Systems. RaghubeeR earned a Master’s in VLSI Design from CDAC Noida and a Master’s in Electronics from DDU Gorakhpur University. RaghubeeR has a solid foundation in various technical areas, including physical synthesis, post-silicon validation, and FPGA design.