Simrata Batra is an experienced VLSI design engineer with a strong background in frontend design and RTL coding in Verilog, as well as circuit/layout design and backend design convergence. They worked at Intel from 2008 to 2014, first as a Component Design Engineer and then as a Silicon Architecture Engineer, focusing on physical design, timing analysis, and micro-architectural optimization. From 2014 to 2021, Simrata held various roles at STMicroelectronics, ultimately becoming a Group Manager. Simrata earned a Master's degree in Electrical Engineering from the University of Southern California and a B.Tech in Computer Science from Guru Gobind Singh Indraprastha University.
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