Stephane Barillet is a Senior Hardware Digital Design Engineer with over 20 years of experience in RTL design. They have worked for notable companies such as PLDA, Atos, and STMicroelectronics, where they currently focus on SoC Front-End Digital Design. Stephane is skilled in project management and has extensive expertise in FPGA design, along with a background in software development for test applications. They hold a Bachelor of Science in Electrical Engineering from Pierre Emile Martin in Bourges.
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