Tarang Aggarwal is a Technical Lead at STMicroelectronics, where they utilize their extensive expertise in memory design. Previously, Tarang served as a Memory Design Engineer and a subcontractor at STMicroelectronics from 2016 to 2019, focusing on memory power and timing analysis, as well as characterization tasks for advanced technologies. Prior to their role at STMicroelectronics, they worked as an R&D Engineer at Synopsys Inc from 2019 to 2021. Tarang holds a Bachelor of Technology degree in Electrical, Electronics and Communications Engineering from Jamia Millia Islamia, where they graduated with First Class Honours in 2015.
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