Vishal K is a PDK Engineer with over four years of experience in the semiconductor industry, specializing in Pcell design and validation. They have worked at STMicroelectronics as a Technical Leader and PDK Developer, focusing on PDK device library development, quality assurance, and layout automation using Cadence SKILL. Vishal's expertise includes proficiency in Cadence Virtuoso, DRC, LVS, and scripting in Python and Shell. They hold a Bachelor of Technology degree in Electronics and Communication from Silicon Institute of Technology.
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