Yap Sie Ing

Yap Sie Ing is a Staff Engineer at STMicroelectronics, specializing in wire bonding processes and equipment application. With 13 years of experience in IC assembly manufacturing, Yap formulates both mid-term and long-term wirebonder roadmaps in alignment with business needs, and actively participates in the wirebond technical community. Prior to their current role, Yap served as a Senior Wirebond Engineer at Infineon Technologies Singapore, focusing on process improvement and new materials development. Yap holds a Bachelor of Electrical and Computer System Engineering from Monash University.