Zeeshan Ahmad is a Technical Leader at STMicroelectronics, specializing in memory layout design and physical verification with 4 years in TestChip Physical Design since 2021. Prior to this role, Zeeshan spent 9 years as a Senior Memory Layout Engineer at Zia Semiconductor Pvt Ltd, focusing on layout design for SRAM memories and achieving expertise in various technologies including FDSOI and CMOS. Zeeshan holds a Bachelor's degree in Electronics and Communications Engineering from Jamia Millia Islamia. Their skill set encompasses advanced design tools like Virtuoso and Innovus, along with a strong proficiency in Unix commands and Shell Scripting.
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