Alexander Laylo

STATS ChipPAC

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Alexander Laylo

Senior Engineer ( Chip On Wafer - Wafer Level Bonding )

Alexander Laylo is a Senior Engineer specializing in Chip On Wafer technology at JCET Group, where they focus on flip chip attachment and wafer-level bonding. Previously, they served as a Research and Development Engineer at UTAC, where they contributed to the development of lead-free adhesive for Copper clip packages and were an inventor on a US patent related to semiconductor packaging. They have also held positions in production maintenance at Rohm Electronics and process engineering at Amkor Technology, where they managed various stages of semiconductor production. Alexander lays a strong emphasis on process improvement and design specifications in their work.

Location

Yishun, Singapore

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