Laurent Varone

Laurent Varone is an experienced Embedded Systems Engineer specializing in Digital Signal Processing at Swiss Timing Ltd since 2017. Prior to this role, Laurent completed an R&D internship at ROLEX in 2016, during which a master thesis focused on developing an automated system for measuring the amplitude of watch balance wheels using image analysis techniques in MATLAB and C++/OpenCV. Earlier experience includes a position as a Security Officer at Securitas AG while studying. Laurent holds a Master's degree in Communication Systems from EPFL, obtained in 2016, and a Bachelor's degree in the same field from EPFL, completed in 2014. Education was preceded by obtaining Maturité gymnasiale from Collège Claparède between 2006 and 2009.