Harini N

Harini N has extensive experience in physical design and VLSI, currently serving as a Module Lead-Physical Design at Synapse Design Inc. since May 2016, where contributions include implementing physical design flows for critical blocks operating at 1.5GHz. Prior experience includes a role as Senior Design Engineer at Concept2Silicon Systems from October 2013 to December 2015, focusing on block level designs across various technology nodes. Earlier positions include work as an ASIC Design Engineer at Uniquify Inc. from September 2010 to March 2012, managing block level implementation and sign-off checks. Harini N holds a Master’s degree in VLSI from the International Institute of Information Technology Hyderabad and a Bachelor’s degree in Electronics from Jawaharlal Nehru Technological University.