Lovely S. is a skilled engineering professional with extensive experience in physical design engineering. Currently serving as a Senior Design Engineer at Synapse Design Inc. since March 2021, Lovely S. has previously held physical design engineer roles at Altran from March 2019 to February 2021 and Aricent Technologies Holdings Limited from March 2018 to March 2019. Early career experience includes a trainee position at ChipEdge Technologies Pvt Ltd from July 2017 to January 2018. Lovely S. holds a Bachelor of Engineering degree in Electrical, Electronics, and Communications Engineering from North Maharashtra University, completed in 2016.
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