Mahitha V is a physical design engineer with expertise in block level implementation utilizing 7nm/6nm/5nm FINFET technology. Currently a Senior Physical Design Engineer at Synapse Design Inc., Mahitha has developed hands-on experience with EDA tools such as ICC2 and Prime Time, and possesses strong knowledge of place and route concepts as well as Static Timing Analysis (STA). Mahitha previously worked as a Physical Design Engineer at SOCTRONICS TECHNOLOGIES PRIVATE LIMITED from 2018 to 2022 and earned a BTech in Electrical, Electronics and Communications Engineering from SRKR Engineering College in 2018.
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