Sagar Doshi

Sagar Doshi is a seasoned professional in the field of Design for Test (DFT) with extensive experience across multiple companies. Currently serving as a Manager at Synapse Design Inc. since March 2022, Sagar previously held the position of Sr. Staff Engineer at Marvell Technology, focusing on SoC ATPG and Silicon bring-up. Prior roles include serving as a Sr. Tech Lead at Cyient, where Sagar led DFT activities for customer projects, and as a DFT Engineer at Intel Corporation, contributing to MBIST efforts on various projects. Sagar's earlier experience encompasses a DFT Consultant role at Broadcom Limited, covering a range of DFT methodologies, and a DFT Engineer position at eInfochips, which involved various DFT projects and formal verification. Sagar holds an Engineering degree in Electronics from Amravati University, earned from 2005 to 2009.