Harsh Shah

Harsh Shah is a seasoned engineer with extensive experience in design verification, currently serving as a Staff Design Verification Engineer at Synaptics Incorporated since July 2019. In this role, Harsh has designed a mechanism to replicate RTL behavior for realistic traffic generation and led final DV sign-offs for boot ROM across multiple projects. Previously, as a Senior Design Verification Engineer, Harsh focused on SoC integration for ARM Cortex and RISC-V core subsystems and developed frameworks for performance measurement. Earlier in the career as a Design Verification Engineer, Harsh developed testbenches aimed at achieving full code and functional coverage. Harsh also gained initial experience as a Design Team Intern at Secutech Automation, where responsibilities included studying building automation systems and utilizing AutoCAD for system design. Harsh holds a Master of Science in Computer Engineering from North Carolina State University and a Bachelor of Engineering in Electrical and Electronics Engineering from D.J. Sanghvi College of Engineering.