Ujjaval Vyas

Ujjaval Vyas is a Senior ASIC Design Engineer at Synaptics Incorporated, with experience beginning in July 2018. Prior to this role, Ujjaval was an ASIC Design Intern at the same company. Ujjaval served as a Teaching Associate at San Jose State University from August 2017 to May 2018, where responsibilities included teaching Python for complex numerical problem-solving and assisting students with Digital Logic and Verilog HDL coding, as well as LTSpice circuit analysis. A Technical Intern at Bharat Sanchar Nigam Limited from August 2014 to December 2015, Ujjaval contributed to hardware design and verification, creating a four-port control switch in Verilog HDL and aiding in C++ application development for debugging purposes. Ujjaval holds a Master’s degree in Electrical and Electronics Engineering from San José State University and a Bachelor of Engineering in Electrical, Electronics, and Communications Engineering from Vishwakarma Government Engineering College, complemented by a Diploma in the same field from Government Polytechnic College, Ahmedabad.