Yogesh Sehrawat

Yogesh Sehrawat is an ASIC architect and designer with over 8 years of experience in developing micro architecture and RTL design for Wi-Fi (PHY) chipsets. They have held positions at Qualcomm as a Senior Lead Design Engineer and Staff Design Engineer at Synaptics, contributing significantly to WLAN PHY hardware design and architecture. Their expertise includes implementing complex digital designs and overseeing the complete ASIC development cycle. Yogesh earned a Master's degree in Electronic Systems Engineering from the Indian Institute of Science in 2017.