Tom Repa

Tom Repa is a highly experienced Digital ASIC and FPGA Designer with over 30 years in logic design and synthesis. They have worked on a diverse array of projects, including the design of gigabit Ethernet and Fibre Channel aggregation logic and the development of multi-channel DMA engines. Tom has held several significant positions, including Principal Engineer at Force10 Networks and Senior Design Engineer at Teledyne LeCroy. Currently, Tom is a Senior Design Engineer at Tachyum. They hold a B.Sc in Physics from Northern Illinois University.