Manasa P is a Senior R&D Hardware Design Engineer at Tejas Networks in Bangalore, with over four years of experience in high-speed circuit design. Previously, Manasa held the position of R&D Hardware Design Engineer at Tejas Networks and was a Member of Technical Staff at Saankhya Labs Pvt. Ltd. Manasa completed a Bachelor of Engineering in Electronics and Communication Engineering from St Joseph Engineering College, achieving an 8.5 CGPA, and also excelled in the PUC program at Ambika Padavi Poorva Vidyalaya Nellikatte Puttur.
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