Mauro Gioi

Mauro Gioi possesses a strong background in hardware engineering, currently serving as an Ingegnere hardware RF at Telit Cinterion since March 2022. Prior experience includes roles as an Ingegnere hardware - sviluppatore FPGA at both Teoresi Group and Leonardo from October 2019 to March 2022. Mauro Gioi holds a Laurea Magistrale LM in Ingegneria elettronica, obtained from Università degli Studi di Cagliari, and a 1° livello - Laurea L in the same field, completed at the same institution. Educational achievements span from 2008 to 2019 within the realm of electronic engineering.