Peter D'Antonio

Peter D'Antonio is an experienced Semiconductor Design Engineer currently at Teradyne since November 2015, providing support for over 100 users in digital design and verification, focusing on version control, IP management, and EDA tool optimization. Previously, Peter served as Principal ASIC Design Engineer at Cognitive Electronics from October 2012 to October 2015, where leadership and expertise were instrumental in building a design and verification team for a multi-core SoC ASIC project. Prior roles include Lead Digital/Microelectronics Hardware Engineer at MITRE, contributing significantly to the development of three timely and successful SoC ASICs, and various engineering positions at Teradyne from June 2000 to April 2007, which encompassed FPGA design, ASIC verification, and digital test development. Peter earned a Bachelor of Science in Electrical Engineering from Cornell University in 2000.