Roger Bartley

Roger Bartley is an accomplished engineering professional with extensive experience in mixed-signal ASIC design and leadership roles. Currently serving as a Senior ASIC Chip Lead at Teradyne since August 2021, Roger previously held significant positions such as Senior ASIC Architect and Design Center Manager at ASIC North, and Principal Design Engineer at Triad Semiconductor. A prior tenure at Teradyne included the role of Engineering Manager for Mixed-Signal ASICs. With a foundational career that began at Tellabs, Roger has contributed to various aspects of ASIC design, including telecommunication ICs, and operated Bartley Consulting, providing design consulting services. Roger holds multiple degrees in Electrical Engineering from the Rose-Hulman Institute of Technology, including a Master's degree in Electrical Engineering as well as degrees in VLSI and DSP.