Arya S

Arya S is a Sr. Silicon Validation Engineer 1 currently employed at Tessolve, where they focus on power rail stress testing for server platforms. Previously, Arya held the position of Silicon Validation Engineer 2 at Tessolve, where they conducted extensive stress testing of SoC designs and performed statistical data analysis. Before joining Tessolve, Arya worked as an Associate Validation Engineer 2 at UST, testing UEFI/BIOS firmware across various hardware platforms and developing test plans within Agile methodologies. With a strong background in x86 architecture and proficiency in C and Python, Arya demonstrates expertise in validation and firmware integration.