Bhargavi Katla

Bhargavi Katla is a Physical Verification Engineer with experience in chip design across TSMC's advanced nodes, ranging from 14nm to 3nm. They worked at Si2chip Technologies Pvt. Ltd. as an Associate Design Engineer, where they focused on fixing DRC/LVS issues at the block level. Subsequently, they held positions at P2F Semi and are currently a Senior Design Engineer at Tessolve, responsible for physical design and verification checks at multiple technology nodes. Bhargavi holds a Bachelor of Technology in Electrical and Communication Engineering from Sridevi Women's Engineering College and is passionate about continuous learning in semiconductor technologies and flow optimization in design signoff methodologies.