Fakeeresh Badiger

Fakeeresh Badiger is a skilled engineering professional with extensive experience in post-silicon validation, currently serving as the Lead - V93K ATE Test Engineer at Tessolve since July 2016. Prior roles at Tessolve include Senior Post Silicon Validation Engineer and Silicon Validation Engineer. Fakeeresh Badiger began a career as a Project Trainee at Central Research Laboratory, BEL, Bangalore, where M. Tech project work was undertaken from August 2014 to May 2015. Educational qualifications include a Master of Technology in Digital Communication from Ramaiah Institute of Technology, completed between 2013 and 2015.