Jeevitha S

Jeevitha S is a Design Lead at Tessolve Semiconductors Pvt Ltd, specializing in analog technology development for Texas Instruments. They have over six years of experience in higher nodes technology, with expertise in creating PCELLs using Cadence PCELL Designer and a solid background in VLSI design and fabrication processes. Previously, Jeevitha held positions as a Senior Layout Engineer at Sankalp Semiconductor and Technical Lead at HCLTech. They also completed a Bachelor's degree in Electrical and Electronics Engineering from Visvesvaraya Technological University.