Mukesh Patel is a Digital Design Engineer currently serving as a Sr. Design Lead at Tessolve since 2025. Prior to this role, Mukesh worked as a VLSI Engineer at Wipro from 2021 to 2025, specializing in FPGA prototyping. Mukesh's earlier experience includes FPGA design positions at Velmenni, where they contributed to a LiFi-based system, and at Anayatech Systems Pvt. Ltd., focusing on various FPGA and microcontroller projects. Mukesh holds a Bachelor of Technology in Electronics and Communication from Krishana Engineering College, earned in 2014.
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