Ritesh Rudragouda is a VLSI Lead Physical Design Engineer currently working at Tessolve, with experience spanning several leading semiconductor companies. They have worked on advanced technology nodes ranging from 3nm to 16nm and have expertise in handling blocks, IPs, and full chip designs. In previous roles, Ritesh served as a Physical Design Engineer at AMD, Qualcomm, Rambus, and ACL Digital, as well as an Associate Engineer at Samsung Semiconductor. They have been involved in processes such as RTL2GDSII, PNR flow, STA, and timing signoff throughout their career.
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