Sumathi Reddy

Sumathi Reddy is a Design Lead at Tessolve, with over six years of experience in design and verification, specializing in IP and SOC verification. Previously, they held engineering roles at Centum Electronics Ltd., Capgemini Engineering, Cyient, HCL Technologies, and Tata Technologies. Sumathi earned a Master of Technology in VLSI Design and Embedded Systems from Visvesvaraya Technological University in 2016 and possesses knowledge in Python, Big Data, and Hadoop, as well as proficiency in VHDL, Verilog, System Verilog, UVM, Perl, TCL, and ICL/PDL.