Dharmendra Mani Varma

Dharmendra Mani Varma is a Memory Design Engineer at TSMC, currently working on SRAM design, including correlation activities for memory performance and debugging circuit timing issues. With over 9 years of experience, they previously held roles at Intel Corporation, Synopsys Inc, and IBM, gaining expertise in memory circuit design and troubleshooting. Dharmendra obtained an M.Tech in Microelectronics from the Indian Institute of Information Technology and has also completed an Honor Code Certificate Course in Circuits and Electronics from the Massachusetts Institute of Technology. They are actively seeking new opportunities, emphasizing that location is flexible for the right role.