Joseph W.

Joseph W. is a SRAM circuit designer at TSMC, specializing in low power and high-density SRAM circuit design and process integration of advanced technologies. They have developed high-density SRAM circuits from 5nm to 3nm technology nodes and possess knowledge of CMOS logic circuits, front-end and back-end process integration, and yield enhancement. Prior to TSMC, Joseph served as a Teaching Assistant at National Taiwan University from 2006 to 2010, and they earned a Ph.D. in Opto-electronics and Photonics from the same institution in 2012. They hold a Bachelor's degree in Electrical and Electronics Engineering from National Tsing Hua University, completed in 2006.